Integrated circuit (IC) devices typically include discrete circuit elements, e.g., transistors, capacitors and resistors, which require interconnect structures to electrically couple or connect the discrete circuit elements into functional circuits. Typical middle of line (MOL) and back end of line (BEOL) metal interconnects may include a wiring line portion and a via portion; however, as technology nodes scale downwards, the interconnect structures become more challenging to fabricate due to the critical dimension (CD) scaling and process capabilities.
By way of example, the interconnect structures are typically fabricated from copper, and may include a barrier layer such as titanium or tantalum or nitride materials such as tantalum nitride or titanium nitride, or a combination thereof. A problem with utilizing copper interconnect structures is that they are highly susceptible to electromigration (EM) which can lead to void formation and failure. One type of EM induced failure is referred to as “line-depletion”, which initiates from the Cu/Dielectric cap interface.
Also, as technology advances, problems arise with filling the interconnect structures, themselves. By way of example, conventional deposition of the TaN/Ta liner and Cu fill beyond a 10 nm node technology is challenging because it cannot provide sufficient coverage of the seed Cu and wider top opening before electro-plating. To this end, an issue is that the metal via fill will impact via void, and impact the die yield and device performance.